Conventionally, the timing control devices in the mobile stations use a high-speed clock when maintaining synchronization with the base stations and when performing continuous reception. On the other hand, the timing control devices use a low-speed clock when they are in a standby state. As the low-speed clock requires less power than the high-speed clock, less power is consumed in the standby state. In order to make the transition into the intermittent reception smoothly, before the transition into the intermittent reception, frequency deviation between the high-speed clock and the low-speed clock is calculated in advance, and the low speed clock in which a frequency is corrected based on the calculated result is used at the sleep time in the intermittent reception time.
The high-speed clock is generally generated using the temperature compensated crystal oscillator (hereinafter, “TCXO”), moreover, the frequency (which is several ppm) of the high-speed clock is stable. On the contrary, the frequency (which is about 100 ppm) of the low-speed clock, like the Real Time Clock (hereinafter, “RTC”) for operating a clock function, easily varies with the temperature. In other words, the low-speed clock is not very stable. Accordingly, when the intermittent reception is repeated for predetermined period, there is more probability of the low-speed clock being affected by the temperature. If the low-speed clock is affected, then the frequency of the clock differs from the frequency deviation calculated before the transition.
As is disclosed in Japanese Patent Application Laid-Open Publication No. 10-190568 (radio reception apparatus), for example, conventionally, the frequency deviation of the low-speed clock is periodically calculated by using the high-speed clock within the time where the intermittent reception continues. An outline of the conventional timing control devices in the mobile stations is explained below.
The frequency deviation occurs in Time Division Multiple Access (hereinafter, “TDMA”) mobile communication system in which respective channels are separated by time axis, a Frequency Division Multiple Access (hereinafter, “FDMA”) mobile communication system in which respective channels are separated by frequencies, and a Code Division Multiple Access (hereinafter, “CDMA”) mobile communication system in which respective channels are divided by codes.
FIG. 12 is a block diagram of the conventional timing control device in the mobile station. This timing control device includes a TCXO 10, a phase synchronizer (hereinafter, “PLL”) 20, a timing control unit 30, a low-speed clock generator (hereinafter, “RTC”) 40, and a control unit 50. The timing control unit 30 includes dividers 31 and 32, a frequency deviation correction value calculation unit 33, and a reference timing counter unit 34.
The PLL 20 receives a TCXO clock 10t from the TXCO 10 and generates a reference clock 20t, which is multiplied by a frequency necessary for the timing control unit 30, and outputs the reference clock 20t to the divider 31 and the reference timing counter unit 34 in the timing control unit 30. The PLL 20 receives a PLL control signal 20r from the reference timing counter unit 34 and determines whether the reference clock 20t should be generated, and outputs a TCXO control signal 10r to the TXCO 10. When it is decided that the reference clock 20t is not necessary, the TCXO control signal 10r requests the TCXO. 10 to stop the oscillation. When it is decided that the reference clock 20t is necessary, the TCXO control signal 10r requests the TCXO 10 to oscillate.
The divider 31 divides the reference clock 20t so as to generate a high-speed clock 31t, and outputs it to the frequency deviation correction value calculation unit 33 and the divider 32. The frequency deviation correction value calculation unit 33 calculates a frequency deviation correction value 33t based on the high-speed clock 31t and a low-speed clock 40t which is generated from the RTC 40 steady so as to output it to the reference timing counter unit 34. The divider 32 divides the high-frequency clock 31t so as to generate a reference clock 32t and output it to the reference timing counter unit 34.
The control unit 50 outputs timing of transition from normal reception into sleep time in intermittent reception and end timing of the sleep time as clock switching timing 50t to the reference timing counter unit 34. The clock switching timing 50t which is output when the transition is made from the normal reception into the sleep time in the intermittent reception represents timing of switching from the reference clock 32t into the low-speed clock 40t. The clock switching timing 50t which is output when the sleep time in the intermittent reception is ended represents timing of switching from the low-speed clock 40t into the reference clock 32t. 
The reference timing counter unit 34 generates reference timing 34t which gives operating references of respective parts in the mobile station based on the frequency deviation correction value 33t, the reference clock 32t, and the low-speed clock 40t, so as to supply it to the parts in the mobile station. The reference timing counter unit 34 determines whether the high-speed clock 31t is necessary based on the clock switching timing 50t, and generates the PLL control signal 20r. When the determination is made that the high-speed clock 31t is not necessary, the PLL control signal 20r requests the PLL 20 to stop oscillation, and when the determination is made that the high-speed clock 31t is necessary, the signal 20r requests the PLL 20 to oscillate.
The timing control device operates in the manner explained below. The reference timing counter unit 34 switches the clock from the reference clock 32t into the low-speed clock 40t and from the low-speed clock 40t into the reference clock 32t according to the clock switching timing 50t input from the control unit 50.
The switching from the low-speed clock 40t into the reference clock 32t is carried out due to the transition into the normal reception at the end of the sleep time in the intermittent reception. In this case, before the switching from the low-speed clock 40t into the reference clock 32t, the reference timing counter unit 34 outputs the PLL control signal 20r to the PLL 20, and requests the PLL 20 to start oscillation of the reference clock 20t. The PLL 20 receives the PLL control signal 20r and outputs the TCXO control signal 10r to the TCXO 10 so as to request the TCXO 10 to start oscillation of the TCXO clock 10t. 
As a result, the TCXO clock 10t output from the TCXO 10 is multiplied by a clock required by the timing control unit 30 in the PLL 20 so as to become the reference clock 20t, and is input into the divider 31 and the reference timing counter unit 34 in the timing control unit 30. The divider 31 divides the input reference clock 20t into a clock frequency to be used by the frequency deviation correction value calculation unit 33, and outputs it as the high-speed clock 31t to the frequency deviation correction value calculation unit 33 and the divider 32. The divider 32 divides the input high-speed clock 31t into a clock with such a rate that it is used at the steady time such as continuous reception in reference timing counter unit 34, so as to output it as the reference clock 32t to the reference timing counter unit 34.
The reference timing counter unit 34 counts up a reference timing counter which gives operation reference timing of the mobile station according to the reference clock 32t, and generates a slot pulse, a frame pulse, or the like based on slot timing, frame timing, or the like so as to output the slot pulse or the frame pulse as the reference timing 34t to the parts in the mobile station. That is to say, the maintenance of synchronization with the base station is controlled by using the reference clock 32t generated from the high-frequency clock 31t, so that the normal continuous reception or the like is executed. The frequency deviation correction value calculation unit 33 calculates the frequency deviation of the low-speed clock 40t using the high-speed clock 31t during the normal reception, and outputs the obtained frequency deviation correction value 33t to the reference timing counter unit 34.
On the other hand, the reference timing counter unit 34 executes the switching from the reference clock 32t with high power consumption into the low-speed clock 40t with low power consumption in order to reduce the power consumption at the time of the transition from the normal reception into the sleep time in the intermittent reception. In this case, the reference timing counter unit 34 outputs the PLL control signal 20r to the PLL 20, and requests the PLL 20 to stop the oscillation of the reference clock 20t. The PLL 20 outputs the TCXO control signal 10r to the TCXO 10 according to the request, so as to request the TCXO 10 to stop the oscillation of the TCXO clock 10t. 
The reference timing counter unit 34 corrects the low-speed clock 40t using the frequency deviation correction value 33t, and counts up the reference timing counter which gives the operation reference timing of the mobile station according to the corrected low-speed clock. As a result, the reference timing counter unit 34 supplies the reference timing 34t to the parts and manages end timing of the sleep time.
While the synchronization with the base station is being maintained by using the corrected low-speed clock, the intermittent reception operation is performed. Since the power consumption of the low-speed clock is small, the power consumption at the standby time is reduced. Before the intermittent reception operation is started, the control unit 50 starts the calculation of the sleep time, and outputs the clock switching timing 50t showing the end of the sleep time to the reference timing counter unit 34. This operation is repeated.
FIG. 13 is a flowchart of the intermittent reception operation in the conventional timing control device. At step ST101, the reference timing counter unit 34 counts up the reference timing counter using the clock which is obtained by correcting the low-speed clock 40t using the frequency deviation correction value 33t. When the count reaches the time of the switching from the low-speed clock 40t into the reference clock 32t represented by the clock switching timing 50t from the control unit 50, the sleep time is determined to be ended, and the PLL control signal 20r requests the PLL 20 to release the stop of oscillation.
At step ST102, when the PLL 20 receives the request of the oscillation starting from the PLL control signal 20r, the TCXO control signal 10r requests the TCXO 10 to release the stop of oscillation. The PLL 20 does not start the oscillation operation.
At step ST103, when the TCXO 10 receives the request of the oscillation starting from the TCXO control signal 10r, after the operation of the circuit becomes stable, the TCXO 10 starts output of the TCXO clock 10t. When the TCXO clock 10t is input into the PLL 20, the PLL 20 starts the oscillation operation for multiplying the TCXO clock 10t, and after the operation becomes stable, it outputs the multiplied reference clock 20t. When the reference clock 20t is output, the parts in the mobile station are ready for starting an operation. The high-frequency clock 31t is input into the frequency deviation correction value calculation unit 33 via the divider 31, and the calculation unit 33 starts to obtain the frequency deviation correction value 33t. When the reference clock 32t is input into the reference timing counter unit 34 via the dividers 31 and 32, the unit 34 switches the clock used for the counting-up of the reference timing counter from the low-speed clock 40t into the reference clock 32t. 
At step ST104, the frequency deviation correction value calculation unit 33 generates a pulse width corresponding to 8192 clock of the low-speed clock 40t with 32.768 kilohertzs, and counts the pulse width using the high-speed clock 31t with 30.72 megahertzs. The calculation unit 33 obtains an average frequency deviation correction value 33t per one clock of the low-speed clock from a difference between the count and a counter number 7680000 at the time of no deviation, so as to output it to the reference timing counter unit 34.
At step ST105, the control unit 50 detects paging information of its own station from polling information from the base station. When its own station is not called, the control unit 50 instructs time that sleep time again comes and time that the sleep time is ended to the reference timing counter unit 34 using the clock switching timing 50t. When the counter value reaches the time of the switching from the reference clock 32t into the low-speed clock 40t shown by the clock switching timing 50t, the reference timing counter unit 34 switches the clock used for the counting-up operation from the reference clock 32t into the low-speed clock which is obtained by correcting the low-speed clock 40t using the frequency deviation correction value 33t. When the polling information from the base station includes the paging of its own station, the transition is made directly into the normal communication state without the transition into the sleep time.
At step ST106, the reference timing counter unit 34 requests the PLL 20 to stop oscillation using the PLL control signal 20r. At step ST107, when the PLL 20 receives the request of the oscillation stop from the PLL control signal 20r, after the PLL 20 stops the oscillation of the reference clock 20t, it requests the TCXO. 10 to stop oscillation using the TCXO control signal 10r. When the TCXO 10 receives the request of the oscillation stop from the TCXO control signal 10r, it stops output of the TCXO clock 10t. Thereafter, the control returns to step ST101. During the intermittent reception operation, the same operation is repeated.
A state at the time of the intermittent reception operation is shown in FIG. 14. FIG. 14 is a time chart of the intermittent reception operation. An intermittent reception period 131 includes reception time 132, sleep time 133, TCXO oscillation stable time 134, and PLL oscillation stable time 135. At the reception time 132, the polling information sent from the base station is received and a determination is made whether its destination is its own station using the reference clock 32t. When the received polling information does not include the paging of its own station, the clock is switched into the low-speed clock after the reception time 132 passes, and the sleep time 133 is started. The TCXO oscillation stable time 134 is until the TCXO 10 actuated at the end of the sleep time 133 can output the stable TCXO clock 10t. The PLL oscillation stable time 135 is until the PLL 20 actuated by the TCXO clock 10t can output the stable reference clock 20t. 
At the reception standby time, the reference clock 32 is used only for the reception time 132 where the polling information is sent from the base station, and the low-speed clock 40t with the low power consumption is used for the following sleep time 133. As a result, the power consumption is reduced.
In the conventional timing control apparatus, the frequency deviation of the low-speed clock with low frequency stability is calculated in advance by using the high-speed clock with high frequency stability, and the deviation of the low-speed clock which is used at the sleep time in the intermittent reception time is corrected by a corrected value of the obtained frequency deviation. As a result, the timing management can be maintained accurately during the intermittent reception.
During the intermittent reception time, however, the frequency deviation of the low-speed clock with low frequency stability is required to be periodically calculated by the calculation of the corrected value using the high-speed clock with high frequency stability. As a result, the power consumption consumed by the calculation of the corrected value cannot be reduced.
It is an object of the present invention to at least solve the problems in the conventional technology.